A parity check circuit is a circuit employable for conducting a parity check which is defined as a test system employable for detecting a bit error of a piece of binary information which bit error has been introduced in the piece of binary information during a period in which the piece of binary information was transmitted. The parity check system is based on a concept to find a bit error by inspecting whether the cumulative number of 1s or 0s included in a transmitted piece of binary information is even or odd, on the premise that all the pieces of binary information to be transmitted are designed to have 1s and 0s of which the cumulative number is even or odd, such a numeral combination being realized by selectively adding 1 or 0 to the original piece of binary information which has the number of bits which is the final bit quantity less 1.
It is inherently difficult to entirely prohibit a bit error from occurring for a piece of binary information in a transmission line, because a bit error is readily caused by a noise picked up during a transmission period in the transmission line.
In order to secure the security of communication, a test system employable for inspecting safe delivery of a piece of binary information is essential. The parity check system is the most prevailing one developed for the purpose.
Referring to FIGS. 1 and 2, a brief description will be presented below for a parity check system and a parity check circuit available in the prior art.
Referring to FIG. 1, a parity check circuit employable for a four-bit binary information available in the prior art is composed of two EXCLUSIVE-OR circuits (1) and (2) constituting the first stage gate, an EXCLUSIVE-OR circuit (5) constituting the second stage gate and an error detector (10).
It is noted that an EXCLUSIVE-OR circuit is a gate which outputs 0, if it is inputted two same signals, namely two 1s or two 0s, and which outputs 1, if the inputted two signals are different from each other, namely e.g. one 1 and one 0. The error detector (10) has a function to output an error signal in response to an output of the EXCLUSIVE-OR circuit of the last stage. The error signals are usually designed to be outputted simultaneously with a clock signal.
Supposing the parity check circuit of FIG. 1 is designed on the basis of the even parity or on the basis that a piece of binary information has a cumulative number of 1s which is even, the gate (5) outputs 0, if the cumulative number of 1s included in an inputted piece of binary information, a combination of A, B, C and D, is even, to show the transmission was normal. And the error detector (10) does not output an error signal. On the contrary, if the cumulative number of 1s included in an inputted piece of binary information, a combination of A, B, C and D, is odd, the gate (5) outputs (1) to show the transmission was abnormal. And this error detector (10) outputs an error signal.
Referring to FIG. 2, a parity check circuit employable for a eight-bit binary information available in the prior art is composed of four EXCLUSIVE -OR circuits (1), (2), (3) and (4) constituting the first stage gate, two EXCLUSIVE -OR circuits (5) and (6) constituting the second stage, an EXCLUSIVE -OR circuit (7) constituting the third stage and an error detector (10).
The quantity of the stages can be determined employing a formula: EQU (Quantity of stages)=log.sub.2 N
wherein, N is the number of bits.
The more the quantity of the bits is, the more the quantity of the stages is. As a result, the time required for inspection of one piece of binary information is determined by a product of the quantity of the stages and the time required for passing through one stage. The more the quantity of the stages is, the longer the time required for inspection of one piece of binary information is. In other words, the time required for inspection of one piece of binary information increases in proportion to the quantity of the stages. Since the period of error detection is determined by the quantity of the stages, the quantity of the stages is a parameter to determine the information transmission rate for a system.